Flash memory cells have enjoyed recent commercial success due to their relatively low cost, the ease in erasing information stored in a flash memory array and their applications to bank check cards, credit cards, and the like. There is no current industry standard flash memory cell. Many types of flash memories exist which embody many different architectures. The programming, reading and erasing of cells can be generally described under one of the following architectures—NOR, AND, or NAND. Further, the programming mechanism of the flash memory cell typically involves Fowler-Nordheim tunneling through an energy barrier or electron injection over an energy barrier.
The array erase mechanism for Fowler-Nordheim cells can involve floating gate to channel, floating gate to drain or floating gate to source as the charge clearing path from the floating gate. The floating gate to drain or source path can prove deleterious to cell operation by destroying the tunnel oxide area located between the floating gate overlap and the drain/source region. The tunnel oxide may also be destroyed through the Fowler-Nordheim programming mechanism or by electron injection (e.g., programming a logic one or logic zero on the floating gate) of conventional flash cells. These programming mechanisms may include charge carrier paths between the floating gate and drain or alternatively between the floating gate and source. However, conventional cells in NOR or AND architectures do not include a programming operation involving a path between the channel and floating gate. Such an operation would be desirable from a standpoint of limiting tunnel oxide degradation due to the field re-distribution effect across the entire tunnel oxide region. In my U.S. Pat. No. 6,307,781 I disclose and claim a triple well structure for a floating gate transistor that permits uniform channel programming. That structure reduces tunnel oxide damage by permitting a uniform voltage across the channel during programming and erasing.
Flash memory cells are often fabricated on the same substrate with logic or linear transistors. In order to have an efficient manufacturing process, the transistors for the control gate in the flash memory cells and the logic and linear transistors often share the same polysilicon mask. They also share the same sidewall oxidation process and the same reactive ion etch (RIE) of the gate. While the sharing of common steps is efficient, it also presents one or more technical problems. As features sizes shrink, logic and/or linear transistors require ultra shallow source and drain junction formation to avoid short channel effect (SCE). In order to achieve such ultra shallow source and drain junction formation the thermal budget for manufacturing the device must be kept very low. In my copending U.S. patent application Ser. No. 10/234,344, filed Sep. 4, 2002 I disclose a method for making flash memories and logic and linear devices on the same substrate.
Despite the above developments, there still remain a number of problems for integrating non-volatile memory technology with conventional CMOS logic and linear devices and processes. I have found that uniform channel programming as employed in NAND or AND architectures extend the scaling limit of memory technology because no voltage differential is applied between the drain and the source during programming or erasing. That is, the bias for the source, the drain, and the well are the same, Vsource=Vdrain=Vwell. However, NAND devices suffer from slow reading times due to their inherent serial access mode. In addition; AND devices require dedicated and separate source and drain bit lines. As such, the conventional metal pitch of an AND memory device requires two metal lines with space in between them in order to separate the source bit line from the drain bit line. Other problems with prior art combination devices is that conventional uniform channel programming in such devices share a well for a common body contact. This common body contact may cause gate induced drain leakage current during programing among the unselected cells. With prior art flash memory devices, a single power supply was provides for VCC. All voltages used in the devices were generated on-board and they require large charge pump areas to sustain the leakage due to the gate induced drain leakage. Also, certain high voltage devices when formed on the same substrate, require or use conventional shallow trench isolation and need large N+/N+ spacing. In other words, they need large peripheral areas.
No one prior art solution addresses all of these problems. It is known in certain uniform channel programming architecture that one may provide N+ buried bit lines. It is also known that the spacing between surface bit lines can be improved by arranging the lines in a jogged manner or by jogging the source and drain contacts. Still others have used isolated P-wells and/or local P-well technology. However, no one of these prior techniques addresses all of the issues raised above.